The present invention relates generally to thermal dissipation in output stages for integrated circuits, and more particularly to segmenting high-current P-channel transistors and high-current N-channel transistors of various integrated circuits such as amplifiers and H-bridge circuits and alternating or “interdigitating” the segmented sections to reduce peak temperatures in the transistors. The invention also relates to providing a uniform temperature profile in the integrated circuit chip and to reducing harmonic distortion and noise and undesirable thermal shutdown caused by excessive peak temperatures and/or thermal gradients caused thereby in an integrated circuit.
In general, the temperatures in regions of integrated circuit output stages in which N-channel output transistors are located are substantially higher than the temperatures in regions in which P-channel output transistors designed to conduct the same amount of current are located. This is because the amount of integrated circuit chip area occupied by an N-channel transistor of a particular current-carrying capability is much lower than the amount of chip area occupied by a P-channel transistor of the same current-carrying capability. The heat generated in an N-channel transistor conducting a high current must flow through the thermal resistance between the chip area occupied by the N-channel transistor and the bottom surface of the chip which is “die bonded” to a metal lead frame through which the heat must be dissipated to prevent excessively high temperature in the transistor. The thermal resistance is inversely proportional to the chip area occupied the transistor. Consequently, heat generated in the inherently-smaller-area N-channel transistor must flow through thermal resistance which is much higher than the thermal resistance through which heat generated in the higher area P-channel transistor must flow, so the temperature in the N-channel transistor may be much higher than in the P-channel transistor conducting the same amount of current. This causes thermal gradients which are different across the chip. It is known that thermal feedback resulting from such thermal gradients can cause changes in offset voltages and create nonlinear offset shifts that cause signal distortion.
More specifically, the power generated in the N-channel or P-channel transistor is equal to the current flowing through the transistor multiplied by its drain-source voltage VDS. The area of the N-channel transistor is roughly one-third to one-fourth the area of a P-channel transistor having the same current-carrying capability, depending on the integrated circuit manufacturing process being used. Therefore, the thermal resistance between the N-channel transistor and the back of the chip is much higher than the thermal resistance between the P-channel transistor and the back of the chip, so heat generated in the N-channel transistor does not flow through the thermal resistance nearly rapidly as from the P-channel transistor to the lead frame. Consequently, the temperature of the N-channel transistor may rise to a much higher level, resulting in “hot spots” in the N-channel transistors during high current operation (while the rest of the chip remains at a much lower temperature). The hot spots can result in destruction of the N-channel transistor.
The maximum acceptable temperature for any transistor in many CMOS integrated circuit chip designs is approximately 150 degrees centigrade. To prevent destruction of the N-channel transistor peak temperatures above 150 degrees centigrade, many integrated circuits include thermal shutdown circuits that detect excessively high temperature in high-power N-channel output transistors and automatically “shut down” the integrated circuit by turning off the output transistors before a critical temperature sufficiently high to cause destruction of the integrated circuit is reached.
Until now, the main solutions to the foregoing problem have been to either de-rate the maximum operating power of the integrated circuit or to use a “thermal spreader” such as a beryllium or copper pad or substrate attached between the bottom of the integrated circuit chip and the lead frame to which the chip is attached. However, de-rating the maximum operating power reduces the number of applications in which the integrated circuit can be used and also reduces the price that the market is willing to pay for the integrated circuit. And using a thermal spreader or heat sink is undesirably costly.
It would be very desirable to avoid the need for an integrated circuit to go into a thermal shutdown mode as a result of the temperature of a single N-channel output transistor becoming unacceptably high while the rest of the integrated circuit remains at a much lower and completely safe operating temperature.
There is an unmet need for an improved integrated circuit that avoids the occurrence of premature “hot spots” in N-channel transistors of complementary output circuit stages.
There also is an unmet need for an improved integrated circuit that inexpensively avoids premature thermal shutdown without substantially increasing the cost of the integrated circuit.
There also is an unmet need for an integrated circuit output stage having complementary N-channel and P-channel output transistors which avoids the need to use thermal spreaders or heat sinks, such as beryllium or copper thermal spreaders, in order to avoid excessively high hot spot temperatures.
There also is an unmet need for an integrated circuit output stage having complementary N-channel and P-channel output transistors which avoids the need to de-rate the maximum operating power of the integrated circuit in order to avoid the premature occurrence of excessively high hot spot temperatures.
There also is an unmet need to create uniform temperature gradients emanating from an integrated circuit output stage to avoid temperature distortions affecting offsets and thereby causing various degradations of circuit performance.